Ihre Tätigkeiten

Prepare verification plans aiming to cover requirements and typical weaknesses of digital systems composed of clocking, interfaces and large digital content
Work closely with designers and concept to achieve high quality deliveries
Constantly align with analog and post silicon counter parts to achieve the highest synergies in targets, implementations and methods
Offer cutting-edge verification solutions to concept and design leads
Contribute to innovation projects in the field of AI/Machine Learning with focus on automation of the mixed-signal verification working flow
Analyze verification regression results to provide analytics on coverage
Prepare and provide state of the art documentation for verification deliveries

Ihr Profil

A degree in Electronic Engineering, Microelectronics , or equivalent field of studies
At least 5 years of experience in mixed-signal and digital verification of IC designs or equivalent verification field
Good experience with EDA tools for mixed-signal and digital verification (Cadence AMS-Designer/XCelium, Synopsys VCS/XA) and test bench concepts and methodologies (UVM)
Profound knowledge of standard SW programming languages, HDL languages (focus on System Verilog), plus the ability to write synthesize-able, behavioral code and real-number modelling
Ability to implement and test scripts (Python, Perl, Shell)
An independent and autonomous working style , with the ability to collaborate effectively within an international team
Fluency in English